Samsung says it has cracked the hardest problem in AI memory manufacturing. On August 26, 2026, the company confirmed it has hit roughly an 80% “golden yield” on HBM4, the next-generation high-bandwidth memory that Nvidia’s upcoming Rubin GPUs depend on, according to Blocks & Files. SK Hynix and Micron are racing to match that output. Together, the three companies are now shipping HBM4 at volumes that were still lab-bound a year ago, and the ramp is arriving just as Nvidia needs it most.
This is not a routine memory refresh. HBM4 doubles the interface width of its predecessor, reshapes how AI accelerators are built, and sits at the center of a supply chain fight that already stretches from Seoul to Boise to Santa Clara. Below is what actually changed this week, what the numbers mean, and where the AI hardware market goes from here.
What Is HBM4, and Why Does It Matter Right Now
High-bandwidth memory (HBM) stacks DRAM dies vertically and connects them to a processor through a silicon interposer, cutting the distance data has to travel compared with conventional GDDR memory sitting on a circuit board. Every generation trades higher bandwidth and capacity for tighter manufacturing tolerances. HBM4, the fourth full generation, widens the data interface from 1,024 to 2,048 I/O connections per stack, according to TechPowerUp. That doubled bus width is the single biggest architectural change since HBM launched in 2013.
The timing lines up with Nvidia’s shift from Blackwell to Rubin, the GPU architecture built to handle what Nvidia calls agentic AI workloads: models that plan, call tools, and run multi-step reasoning chains rather than answering a single prompt. Those workloads chew through memory bandwidth because they keep larger context windows and more intermediate state resident in GPU memory at once. Nvidia’s own developer blog describes Rubin as a six-chip platform built specifically around that memory demand, per Nvidia’s technical writeup. Without HBM4, Rubin doesn’t hit its design targets.
Samsung’s 80% Yield Number, Explained
Yield is the percentage of manufactured dies that actually work well enough to sell. For a product as complex as a 12-layer or 16-layer memory stack, low yield is the difference between a profitable product line and a money pit. Samsung’s climb to roughly 80% golden yield on HBM4 matters because it’s the number that determines whether the company can ship in volume rather than in token quantities to a handful of favored customers.
Samsung’s commercial HBM4 line reaches up to 3.3 TB/s of bandwidth per stack, which the company describes as a 2.7x jump over HBM3E, with pin speeds between 11.7 and 13.0 Gbps, according to Samsung’s newsroom announcement. The company is offering 24 GB and 36 GB capacities using 12-layer stacking today, with 16-layer stacks up to 48 GB planned. Under the hood, Samsung is pairing sixth-generation 10nm-class DRAM dies with a 4nm logic base die, a combination detailed in ISSCC 2026 conference coverage from SemiAnalysis.
SK Hynix and Micron Aren’t Standing Still
Samsung’s yield milestone is the headline, but it’s not shipping in a vacuum. SK Hynix, which has supplied the bulk of Nvidia’s HBM3E to date, showed a 16-layer HBM4 stack at CES 2026 delivering 48 GB of capacity and roughly 2 TB/s of bandwidth per stack, close to 2.5 times current HBM3E performance, according to CES coverage syndicated through TokenRing’s financial news wire. Reporting from the same event puts a Rubin configuration using eight stacks of SK Hynix’s 48 GB HBM4 at 384 GB of total GPU memory with aggregate bandwidth above 22 TB/s.
Micron, the smallest of the three by HBM market share, is also in high-volume production. Its HBM4 uses a 2,048-pin bus running above 11.0 Gbps per pin for more than 2.8 TB/s of bandwidth per stack, more than double HBM3E, per Micron’s own product page. Micron’s 12-high package ships at 36 GB per stack while holding that same bandwidth figure. Micron has publicly tied this generation to Nvidia’s Vera Rubin platform, along with PCIe Gen6 SSDs and SOCAMM2 memory modules for the same systems.
HBM4 vs. HBM3E: The Bandwidth and Capacity Jump
The generational leap is easiest to see side by side. Here’s how the current HBM3E generation compares with what’s now shipping under the HBM4 label:
| Spec | HBM3E | HBM4 |
|---|---|---|
| I/O connections per stack | 1,024 | 2,048 |
| Bandwidth per stack (Samsung) | ~1.2 TB/s | Up to 3.3 TB/s |
| Pin speed | ~9.2 Gbps | 11.7–13.0 Gbps |
| Max stack height | 12-Hi | Up to 16-Hi |
| Max capacity per stack | 36 GB | Up to 48–64 GB |
| JEDEC die density options | 24 Gb | 24 Gb or 36 Gb |
Those numbers come from JEDEC’s published HBM4 standard and vendor spec sheets, cross-referenced via Blocks & Files’ supply chain reporting. The practical upshot: a GPU built with eight HBM4 stacks can carry meaningfully more onboard memory and bandwidth than the same GPU built with HBM3E, without changing the number of stacks or the physical footprint on the package.
Inside Rubin: Why Nvidia Needs This Much Memory
Nvidia’s memory appetite has grown every generation, but Rubin marks a bigger jump than usual. Reported configurations vary by source: some coverage puts a Rubin GPU at up to 288 GB of HBM4 using eight 36 GB stacks, while other reporting describes a 384 GB configuration using eight 48 GB stacks. Both figures show up in current reporting because Nvidia and its memory partners are qualifying multiple stack configurations in parallel rather than locking to a single SKU months before launch.
That memory ceiling matters because agentic AI systems keep more state alive per request: longer context windows, tool-call history, and retrieved documents all sit in GPU memory during inference, not just during training. A model serving agentic workloads at scale can be memory-bound well before it’s compute-bound. That is also why Tom’s Hardware reported that Nvidia has been testing lower-memory Rubin Ultra configurations, including designs with as little as 192 GB, as a hedge against tight HBM4 supply. Nvidia would rather ship a leaner config on time than wait for every stack to arrive at full capacity.
Vendor Scorecard: Samsung, SK Hynix, Micron, and AMD
No single supplier controls this cycle the way SK Hynix dominated early HBM3E. Here’s where each player stands as of late August 2026:
| Company | Reported status | Key spec | Primary customer link |
|---|---|---|---|
| Samsung | ~80% golden yield, commercial shipments | Up to 3.3 TB/s, 24–36 GB/stack | Nvidia Rubin qualification |
| SK Hynix | 16-layer stack demoed at CES 2026 | 48 GB, ~2 TB/s per stack | Nvidia’s largest HBM3E supplier historically |
| Micron | High-volume production announced | 36 GB, >2.8 TB/s per stack | Named directly to Vera Rubin platform |
| AMD (customer side) | Adopting 12-high HBM4 in its own AI chips | 432 GB and 23.3 TB/s reported per chip | Competing AI accelerator line |
The AMD figures come from Chosun Biz’s English-language reporting on AMD’s HBM4 adoption for its own accelerators, a reminder that this memory race isn’t only about Nvidia. Whoever secures HBM4 allocation first gets a real product advantage, because the bottleneck now sits at the memory vendor, not the GPU designer.
The Memory Shortage Feedback Loop
HBM4 doesn’t exist in isolation from the rest of the DRAM market. Samsung, SK Hynix, and Micron are the same three companies that make conventional DDR5 for laptops, desktops, and servers, and all three are redirecting fab capacity toward the higher-margin HBM4 business. That reallocation is a direct contributor to the consumer memory price spike covered in shattered.io’s earlier reporting on RAM prices climbing 89% as gaming and PC buyers compete with AI data centers for the same wafer starts.
It’s a feedback loop with no obvious near-term fix: more AI capex drives more HBM4 orders, which pulls fab capacity away from commodity DRAM, which raises consumer RAM prices, which in turn makes the AI vendors’ margins look even better by comparison since they’re selling a premium product into a supply-constrained market. Analysts tracking GPU shipments put Nvidia’s Blackwell-family shipments (B200, GB200, B300) at roughly 5.2 million units in 2025, falling to about 1.8 million units in 2026 as the product line transitions to Rubin, according to Presenc.ai’s GPU shipment tracker.
Blackwell to Rubin: The Shipment Transition
| Year | Blackwell family (B200/GB200/B300) | Primary memory |
|---|---|---|
| 2025 | ~5.2 million units | HBM3E |
| 2026 | ~1.8 million units (declining as Rubin ramps) | Transition to HBM4 |
A drop of that size in one generation is unusual for Nvidia, whose data center GPU shipments had climbed every year since 2020. It signals that customers are deliberately holding orders back to wait for Rubin’s memory advantage rather than buying more Blackwell capacity in the interim, a pattern that puts even more pressure on HBM4 supply to arrive on schedule.
Historical Context: A Decade From HBM1 to HBM4
High-bandwidth memory has moved fast for a hardware standard. HBM1 launched in 2013 as a niche product for graphics cards. HBM2 and HBM2E carried the first generation of AI accelerators through the late 2010s. HBM3 and HBM3E, which shipped alongside Nvidia’s Hopper and Blackwell GPUs, turned HBM from a graphics niche into the defining bottleneck of the AI boom, with SK Hynix and Samsung locked in a multi-year supply fight that occasionally left Nvidia short of chips it had already sold.
HBM4 is the first generation where JEDEC standardized a genuinely wider interface rather than just pushing pin speeds higher, according to the JEDEC-derived specs cited by Blocks & Files. That’s a structural change, not an incremental one, and it’s part of why yield ramped more slowly than some earlier generations. It also explains why this week’s yield news carries weight: the industry wasn’t sure HBM4 would scale to commercial volumes on the original timeline.
Market Impact: Capex, Margins, and the AI Supply Chain
Memory has quietly become one of the largest line items in AI infrastructure spending. When a single GPU can carry 288 to 384 GB of HBM4, and that memory costs multiples more per gigabyte than commodity DRAM, memory alone can represent a large share of a GPU’s bill of materials. That dynamic already shapes how hyperscalers plan capex. It’s part of the same broader capacity story behind moves like AWS’s recent 2 million-GPU Nvidia deal, where memory availability, not just GPU die supply, increasingly determines how fast cloud providers can deploy new AI capacity.
It also raises the stakes for anyone trying to compete with Nvidia on margin. Reports of OpenAI’s own silicon ambitions, covered in shattered.io’s earlier piece on the so-called Jalapeño chip, face the same constraint: building a competitive AI chip means competing for the same scarce HBM4 allocation that Nvidia, AMD, and every other accelerator vendor are already fighting over. Owning chip design doesn’t help much if the memory supply is the bottleneck.
What This Means for Cloud Providers and Enterprise Buyers
For enterprise teams planning AI infrastructure purchases, the HBM4 ramp changes near-term math in a few concrete ways. First, expect Rubin-based instances from major cloud providers to arrive in multiple memory tiers rather than a single configuration, mirroring the 192 GB to 384 GB spread already showing up in pre-launch reporting. Second, expect pricing on high-memory instances to stay elevated through at least the first half of 2027 while yields climb further and allocation gets rationed toward the largest customers first.
Third, and less obviously, expect on-premises AI hardware buyers to feel this indirectly through component pricing across the board, not just GPUs. The same fabs building HBM4 also build the DDR5 and LPDDR5X used in servers, laptops, and workstations, so hardware refresh budgets planned before this ramp may need revisiting. Teams evaluating local inference setups, including consumer-grade options like running LLMs locally on an RTX 5090, should expect that GPU’s own GDDR7 memory pricing to track the same upward pressure, even though GDDR7 and HBM4 are different products from different production lines.
Competitive Comparison: How the Big Three Stack Up
Samsung’s advantage right now is yield and breadth of capacity options, from 24 GB up to a roadmap for 48 GB stacks. SK Hynix’s advantage is incumbency. It has run Nvidia’s HBM3E supply chain for years and has working relationships that make qualification faster even when its raw specs trail Samsung’s headline bandwidth figure. Micron is the smallest of the three but has moved fastest to tie its HBM4 roadmap explicitly to a named platform (Vera Rubin), which gives it a clearer design-win story even without the largest market share.
None of the three has a clean lead across every metric, and that’s arguably good news for Nvidia and other GPU buyers: a single-vendor bottleneck on HBM3E was one of the reasons AI GPU supply stayed tight through 2024 and 2025. A three-way HBM4 race, even an uneven one, gives Nvidia more leverage to negotiate price and secure redundant supply.
Risks to the Timeline
An 80% yield figure sounds close to mature production, but memory manufacturing at this complexity rarely moves in a straight line. Advanced packaging, specifically the process of bonding 12 or 16 DRAM dies to a logic base die without introducing defects, remains the tightest constraint industry-wide, a point UTMel’s semiconductor analysis flags as the next bottleneck even after core DRAM yield improves. A packaging slip at any one vendor could delay Rubin’s broad availability regardless of how good Samsung’s die-level yield looks in isolation.
Predictions: Where This Goes From Here
- Rubin ships in multiple memory tiers. Expect Nvidia to formally announce at least two Rubin SKUs, a full-memory version near 384 GB for flagship customers and a reduced-memory version closer to 192-288 GB for broader availability, rather than a single spec.
- Consumer DRAM prices stay elevated into 2027. As long as Samsung, SK Hynix, and Micron keep redirecting capacity toward HBM4, expect little relief on DDR5 and laptop memory pricing before mid-2027 at the earliest.
- A fourth HBM4 supplier does not emerge this cycle. The capital and yield requirements are high enough that no new entrant is likely to reach commercial HBM4 volume before 2028, keeping the market a three-way race.
- AMD’s HBM4 accelerators narrow, but don’t close, the memory-capacity gap with Nvidia. Reported AMD figures already rival Rubin’s high-end configuration on paper, which should intensify competition on price per GB rather than raw specs.
- Packaging capacity, not die yield, becomes the next headline bottleneck. Expect the next wave of supply-chain reporting to shift from “can they make the dies” to “can they bond and package them fast enough,” echoing the packaging concerns already raised around ISSCC 2026.
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Frequently Asked Questions
What is HBM4 memory?
HBM4 is the fourth generation of high-bandwidth memory, a type of DRAM stacked vertically and connected to a processor through a silicon interposer. It doubles the data interface width to 2,048 I/O connections per stack compared with HBM3E’s 1,024, enabling higher bandwidth and capacity per stack.
Why does Samsung’s 80% yield number matter?
Yield determines how many manufactured memory stacks are good enough to sell. An 80% “golden yield” means Samsung can move from limited sampling to real commercial volume, which is the threshold Nvidia needs before it can build Rubin GPUs at scale.
How much memory will Nvidia’s Rubin GPUs have?
Reported configurations range from roughly 192 GB in cost-reduced designs up to 384 GB in flagship configurations using eight HBM4 stacks, depending on which stack capacity (36 GB or 48 GB) Nvidia and its partners qualify for a given SKU.
Is HBM4 the reason consumer RAM prices are rising?
It’s a major contributing factor. Samsung, SK Hynix, and Micron are shifting fab capacity toward higher-margin HBM4 production for AI customers, which reduces the wafer capacity available for conventional DDR5 and laptop memory, pushing consumer prices higher.
Which company is ahead in the HBM4 race: Samsung, SK Hynix, or Micron?
No single company leads on every metric. Samsung currently reports the highest yield and bandwidth headline figures. SK Hynix has the deepest existing relationship with Nvidia from the HBM3E era. Micron has moved fastest to name its HBM4 roadmap directly to Nvidia’s Vera Rubin platform.
Does AMD use HBM4 too?
Yes. AMD is adopting 12-high HBM4 in its own AI accelerators, with reported figures of 432 GB of capacity and 23.3 TB/s of bandwidth per chip, putting it in direct competition with Nvidia’s Rubin-class memory configurations.
When will Rubin-based cloud instances be available?
Exact launch timing hasn’t been finalized publicly, but shipment tracking already shows Blackwell-family volumes declining sharply in 2026 as customers hold orders in anticipation of Rubin, suggesting broader Rubin cloud availability is expected to ramp through late 2026 and into 2027.
What’s the biggest remaining risk to the HBM4 rollout?
Advanced packaging, the process of bonding multiple DRAM dies to a logic base die without introducing defects, is considered the next bottleneck even as raw die yield improves, meaning a packaging slip at any vendor could still delay broad Rubin availability.
