Everspin Technologies says it has done something no memory maker has managed before: hook magnetoresistive RAM directly into a server over Compute Express Link, or CXL, and let it behave like a fast, power-loss-proof memory tier instead of a slow storage device. The company demonstrated the setup at the SNIA Developer Conference 2026 on September 29, calling it the world’s first CXL-connected MRAM platform. Everspin says writes on the system ran up to 100 times faster than NAND-based solid-state storage, a company claim rather than an independently verified benchmark.
The timing is not an accident. Data centers building out AI infrastructure are running short on memory in almost every form, from HBM capacity on Nvidia’s newest GPUs to plain DRAM, which now costs more per chip than leading-edge logic silicon. Everspin, a small Chandler, Arizona-based chipmaker trading as NASDAQ: MRAM, is betting that a nonvolatile memory tier riding on CXL can carve out a niche between conventional DRAM and NAND storage, exactly the gap Intel’s Optane tried and failed to fill.
What Everspin Actually Showed at SNIA 2026
The demonstration paired Everspin’s PERSYST 1GB DDR4 MRAM UDIMMs with a CXL controller built by Wolley, running on a Supermicro AS-1116CS-TN server powered by an AMD EPYC 9355 processor and an AMD Alveo U250 FPGA acting as the CXL endpoint. Everspin and Wolley demonstrated read and write access to MRAM through the CXL interface under what the companies described as demanding test conditions, positioning the setup as ready for customer workload testing rather than a finished, shipping product.
Everspin frames the platform as a persistent-memory tier sitting between DRAM and NAND, reachable with normal memory semantics instead of storage commands, and accessible at what it calls cache-line-level, nanosecond-class latency. That framing matters because it draws a direct line to memory, not storage. A CPU core can touch MRAM the way it touches RAM, without going through a block-storage driver, and the data survives a power cycle the way a hard drive’s does. No pricing, shipping date, module capacity beyond the 1GB demo units, or production commitment has been disclosed.
The Hardware Stack, Piece by Piece
- Memory: Everspin PERSYST 1GB DDR4 MRAM UDIMMs
- CXL controller: Wolley
- Accelerator/endpoint: AMD Alveo U250 FPGA
- Server: Supermicro AS-1116CS-TN
- Processor: AMD EPYC 9355, 32 cores
What CXL Is, and Why Memory Needs It
Compute Express Link is a cache-coherent interconnect that rides on the PCI Express physical layer, letting CPUs, accelerators, and memory devices share data without each device needing its own dedicated, fixed wiring to the processor. Three protocols do the work: CXL.io handles ordinary device discovery and configuration, CXL.cache lets a device read host memory coherently, and CXL.mem lets a host processor treat memory sitting on a CXL device as part of its own address space.
That last piece, CXL.mem, is what makes Everspin’s demo possible. Instead of MRAM showing up as a storage volume that needs a filesystem and a driver, it shows up in the memory map, addressable the way DRAM is. In a data center context, CXL also enables memory pooling, where a shared bank of memory attached through a CXL switch can be dynamically carved up and handed to whichever server or accelerator needs it that hour instead of sitting stranded on one machine. Cloud operators care about this because DRAM that is bought but not used on any given server is money spent on nothing. Everspin’s pitch is to bring nonvolatility into that same pooled-memory conversation.
MRAM in Plain Terms: Why Nonvolatile Memory Matters
Magnetoresistive RAM stores a bit as a magnetic state rather than as an electrical charge on a capacitor, which is how DRAM does it. That difference sounds academic, but it changes behavior in two ways that matter to a data center operator. First, MRAM does not need the constant refresh cycles that DRAM requires to keep every bit from leaking away, which cuts a source of standby power draw. Second, and more importantly for this announcement, MRAM keeps its data when the power goes off. A server that loses power mid-write to DRAM loses that data. A server that loses power mid-write to MRAM, in theory, does not, at least for whatever made it into the memory cells before the outage.
STT-MRAM and the Persistent-Memory Pitch
Everspin’s underlying technology is spin-transfer torque MRAM, or STT-MRAM, which the company has shipped in smaller industrial and automotive parts for years. The new piece is not the memory cell itself but the CXL wrapper around it, which is what lets a persistent memory chip present itself to a modern server the same way a bank of DRAM does. Everspin describes the goal as bringing storage-class persistence closer to the processor, cutting the number of hops data has to make between where it is computed and where it is safely kept.
The 100x Faster Claim, and Why It Needs Context
Everspin’s marketing puts writes on the CXL-MRAM platform at up to 100 times faster than writes to NAND-based SSD storage. That is a real gap in kind, not just degree: NAND has to erase a block before it can rewrite it, manage wear leveling across cells, and often buffer writes before confirming them, while MRAM writes directly to a cell with no erase step. A 100x figure in that direction is plausible on paper for small, latency-sensitive writes. What the company has not published is the workload used to generate that number, the queue depth, which specific NAND SSD served as the baseline, the software stack involved, or any independent third-party confirmation. Readers should treat it as a vendor benchmark until someone outside Everspin runs the comparison.
It is also worth separating two different comparisons that are easy to blur. MRAM versus NAND SSD is a fair fight because both are nonvolatile. MRAM versus DRAM is a different question entirely, and Everspin has not claimed to beat DRAM on raw speed. The pitch is that MRAM gets close enough to DRAM-class latency while adding the one thing DRAM cannot do: keep data through a power loss.
Why AI Data Centers Are the Real Audience
None of this would be newsworthy outside a niche electronics trade press if it weren’t landing in the middle of a broader memory squeeze. AI training and inference clusters are consuming DRAM and HBM faster than fabs can add capacity, and the knock-on effects are showing up everywhere from phone bills of materials, where RAM now eats 60% of the device cost, to Chinese memory makers racing to build out DRAM and NAND lines to chase the same demand. Against that backdrop, any technology that promises to move even a slice of a server’s working set off scarce DRAM and onto something cheaper and persistent gets a hearing it might not have gotten in 2021.
Large language model serving in particular generates huge, fast-growing key-value caches that eat DRAM for the duration of a session. A persistent, CXL-attached memory tier that can hold warm or cold context without power-loss risk, and without paying NAND’s latency tax, is a plausible fit for that specific problem, though it remains theoretical until someone runs it at production scale. Analysts have also pointed to projected wafer price increases heading into 2027 as a reason fabs and system builders are looking harder at alternatives to simply buying more DRAM.
Historical Context: Intel’s Optane Warning Label
Anyone pitching a new memory tier between DRAM and storage has to answer for Intel’s Optane first. Intel and Micron co-developed 3D XPoint and Intel sold it as Optane in SSDs and in persistent-memory modules for specific server platforms, chasing precisely the position Everspin is chasing now. Intel announced it was winding the business down on its second-quarter 2022 earnings call, held July 28, 2022, and booked a $559 million Optane impairment charge in that same quarter. The company described the move as portfolio rationalization under its IDM 2.0 strategy, choosing to stop future Optane product development rather than keep funding a line that was not profitable enough to justify the investment.
Optane’s failure was not really about the physics of 3D XPoint. It was about ecosystem lock-in. Optane persistent memory only worked well with specific Intel Xeon platforms, needed application-level awareness to get the most out of it, and competed against NAND SSDs that kept getting faster and cheaper on their own. CXL is Everspin’s answer to exactly that problem: instead of a proprietary Intel-only memory slot, CXL is an open, multi-vendor interconnect that any CPU, FPGA, or accelerator can plug into, at least in principle. Whether that openness is enough to avoid Optane’s fate is the question the next few years will answer.
Everspin’s Business Case: Small Company, Big Swing
Everspin is not a large company betting spare cash on a science project. Shares closed at $18.63 on September 29, 2026, putting the company’s market capitalization at roughly $453.6 million. Its most recent quarter, fiscal Q2 2026, brought in $18.74 million in revenue, and the company has guided to $19.5 million to $20.5 million in revenue for the following quarter. That is a real, profitable-scale niche chipmaker, built mostly on industrial and automotive MRAM sales, not a venture-funded startup burning cash on a moonshot.
That scale cuts both ways for the CXL-MRAM story. On one hand, Everspin does not need this bet to pay off overnight to survive, since its existing MRAM business already generates steady revenue. On the other hand, a company with a market cap under half a billion dollars cannot single-handedly fund the kind of large-scale production, qualification, and hyperscaler courtship that turning a demo into a shipped data-center product requires. Any real volume almost certainly means a partnership with a larger memory, controller, or server vendor, or a customer willing to co-develop and pre-commit to purchase.
Competitive Landscape: Who Else Is Circling CXL Memory
Everspin is not the only company chasing a role in the CXL memory story, though its specific angle, nonvolatile MRAM riding CXL, appears to be genuinely novel rather than a me-too move. The broader CXL memory-expansion space includes larger memory makers building volatile CXL memory modules meant to pool and extend standard DRAM rather than replace it with something persistent. Those products, generally described in the press as adding memory capacity and bandwidth to CPUs without requiring a new socket, address a related but distinct problem: not enough DRAM per server, rather than DRAM’s lack of persistence.
Nonvolatile vs. Volatile CXL Approaches
That split is worth keeping straight. A volatile CXL memory expander gives a server more DRAM-equivalent capacity, full stop, and loses everything on power loss just like ordinary DRAM. Everspin’s nonvolatile CXL-MRAM gives a server less capacity per module today, since the demo units are 1GB parts, but adds a persistence guarantee that no DRAM-based CXL product can match. The two approaches are not head-to-head competitors so much as adjacent answers to different halves of the same memory-capacity problem facing AI infrastructure.
Market Impact: What This Means for Buyers and Cloud Operators
For the cloud providers and hyperscalers actually buying memory at scale, a single-vendor demo with 1GB modules changes nothing about this week’s procurement decisions. What it does is add one more data point to a trend line: memory is scarce enough, and expensive enough, that buyers are willing to evaluate architectures they would have ignored two years ago. That same pressure shows up in consumer devices, where memory now accounts for a majority of some laptops’ bill of materials, and in warnings from chipmakers that meaningful relief is not close.
Everspin’s stock is a useful, if imperfect, gauge of how the market is pricing this news. A sub-$500 million company demonstrating early-stage, unpriced, uncommitted technology is not the kind of event that moves index funds, but it is exactly the kind of announcement that can move a small-cap stock sharply in either direction as traders try to guess whether a partnership or design win follows. Investors should read the September 29 demo as proof of concept, not proof of revenue.
What Everspin and Its Partners Are Saying
Everspin has been telegraphing this work for more than a year. On an earlier earnings call, the company said: “As a next step, we are in the process of demonstrating Computer Express Link, or CXL, STT-MRAM,” according to a transcript of that call. The same call included the company’s rationale for pairing the two technologies: “CXL is an ideal interface for MRAM as it allows utilization of the full range of MRAM benefits whether directly attached or in shared architectures to enable resource sharing within a CXL network,” Everspin said, according to that transcript.
Ahead of the SNIA conference, Everspin previewed the plan directly. “The company plans to demonstrate a new CXL solution at the SNIA Developers Conference in September using an AMD UltraScale plus FPGA-based platform,” Everspin told investors, according to a transcript of its Q2 fiscal 2026 earnings call published by The Motley Fool. On the same call, the company framed the bigger strategic goal behind the demo: “We continue to advance our development work on CXL interface-based MRAM solutions, which will address the demand for nanosecond class persistent memory solutions, bringing storage closer to XPUs, enhancing compute and power efficiency, resulting in significant overall cost savings,” Everspin said, according to that same Motley Fool transcript.
Following the actual demo, coverage of the event described the outcome in direct terms: Everspin demonstrated read and write access to MRAM through the CXL interface under demanding test conditions, as reported by StockTitan’s coverage of the September 29 announcement. None of these statements come from an independent lab or a customer, a limitation worth keeping in mind while reading the rest of the coverage this week.
Persistent Memory Technologies Compared
| Technology | Volatility | Typical Role | Status in Late 2026 |
|---|---|---|---|
| DRAM | Volatile | Primary system memory, closest to CPU | Mainstream, but in short supply and rising in price |
| NAND SSD | Nonvolatile | Bulk storage tier | Mainstream, cheaper per GB than any memory tier |
| HBM | Volatile | GPU-attached, high-bandwidth accelerator memory | Mainstream but capacity-constrained on newest GPUs |
| Intel Optane / 3D XPoint | Nonvolatile | Attempted DRAM-to-NAND gap filler | Discontinued by Intel in July 2022 |
| CXL-attached DRAM expanders | Volatile | Pooled capacity expansion over CXL | Emerging, shipping from several memory vendors |
| Everspin CXL-connected STT-MRAM | Nonvolatile | Proposed DRAM-to-NAND gap filler via CXL | Early demonstration stage, shown Sept. 29, 2026 |
Everspin Technologies at a Glance
| Metric | Figure |
|---|---|
| Ticker | NASDAQ: MRAM |
| Headquarters | Chandler, Arizona |
| Share price (Sept. 29, 2026 close) | $18.63 |
| Approximate market capitalization | $453.6 million |
| Q2 fiscal 2026 revenue | $18.74 million |
| Q3 fiscal 2026 revenue guidance | $19.5M–$20.5M |
| SNIA demo date | September 29, 2026 |
| Demo memory product | PERSYST 1GB DDR4 MRAM UDIMM |
| Demo CXL controller partner | Wolley |
| Claimed write-speed advantage over NAND SSD | Up to 100x (company claim, unverified independently) |
How CXL Memory Shows Up to an Operating System
For engineers who want to know what CXL-attached memory actually looks like from software, the short version is that Linux exposes it through existing device-memory tooling rather than a brand-new interface. A system administrator inspecting a CXL memory device typically works with commands like these, used generically across CXL memory devices rather than specific to Everspin’s demo hardware:
cxl list -M
daxctl list
numactl --hardwareThe cxl list command enumerates CXL memory devices the kernel has recognized, daxctl list shows how that memory is exposed as a device-DAX region for direct application access, and numactl --hardware shows where the new memory sits relative to existing NUMA nodes, which matters because CXL memory typically carries higher latency than locally attached DRAM. None of this is unique to Everspin’s platform. It is the same tooling any CXL.mem device, MRAM-based or otherwise, would need to pass through to be usable by an application.
Predictions: Where CXL-Attached Memory Goes From Here
- More small-vendor demos before hyperscaler adoption. Expect other niche memory makers to show similar CXL-attached persistent-memory proofs of concept over the next year, without a major cloud provider committing to production volume in that window.
- Independent benchmarking pressure grows. Given Optane’s history of underdelivering on early promises, expect analysts and potential customers to push Everspin for third-party validation of the 100x write-speed claim before treating it as a procurement-grade number.
- Capacity, not persistence, remains the nearer-term priority. With HBM and DRAM both tight, volatile CXL memory-expansion products are likely to see faster adoption than nonvolatile CXL-MRAM, simply because raw capacity is the more urgent problem for AI training and inference clusters right now.
- Partnership or acquisition risk for Everspin. A company with Everspin’s roughly $450 million market cap is unlikely to scale a data-center memory product alone. A licensing deal, joint development agreement, or acquisition by a larger memory or systems vendor is a realistic path if the technology gains traction.
- AI inference caching is the first realistic use case. If CXL-MRAM finds an early home anywhere, it is more likely to be as a persistent cache for large language model key-value data or checkpoint state than as a DRAM replacement for general-purpose compute.
Frequently Asked Questions
What did Everspin actually announce on September 29, 2026?
Everspin demonstrated what it calls the world’s first CXL-connected MRAM platform at the SNIA Developer Conference 2026, pairing its PERSYST 1GB DDR4 MRAM UDIMMs with a Wolley CXL controller on a Supermicro server built around an AMD EPYC 9355 processor.
Is CXL-connected MRAM available to buy right now?
No. This was a technology demonstration, not a product launch. Everspin has not disclosed pricing, shipping dates, or production module capacities beyond the 1GB units used in the demo.
Is the “100x faster” claim independently verified?
No. The figure comes from Everspin’s own comparison against NAND-based SSD storage. The company has not published the workload, baseline device, or methodology needed for outside verification.
How is MRAM different from the DRAM in my computer?
DRAM stores data as an electrical charge that needs constant refreshing and disappears when power is lost. MRAM stores data as a magnetic state that does not need refreshing and survives a power cycle, at some cost in density and, historically, in per-bit price compared with DRAM.
Why did Intel’s Optane fail, and is Everspin repeating the mistake?
Intel discontinued Optane in July 2022 after it failed to reach profitable scale, in part because it only worked well with specific Intel server platforms. Everspin is betting that building on the open, multi-vendor CXL standard instead of a proprietary interface avoids that specific failure mode, though the broader challenge of proving commercial demand remains unresolved.
What is Everspin’s stock ticker and how big is the company?
Everspin trades on Nasdaq as MRAM. Shares closed at $18.63 on September 29, 2026, giving the company a market capitalization of roughly $453.6 million, with $18.74 million in revenue reported for fiscal Q2 2026.
Why does AI infrastructure care about a small memory startup’s demo?
AI data centers are running short on DRAM and HBM capacity, driving up costs across the industry. Any technology that credibly offers a cheaper, persistent alternative for part of that memory footprint draws attention, even at an early, unpriced demonstration stage.
Who else is working on CXL-attached memory?
Several larger memory vendors have shipped or previewed volatile CXL memory-expansion modules that add DRAM-equivalent capacity to servers over the CXL interconnect. Those products target capacity shortages rather than persistence, making them a complement to, rather than a direct competitor of, Everspin’s nonvolatile approach.
