Arm vs x86 in AI Servers: 3B Beats 4.6B [2026]

Will x86 servers disappear?

No forecast in the current data points to that. x86 still holds roughly half of hyperscaler compute share, and AMD’s Venice and Intel’s Clearwater Forest are both real, shipping products aimed at defending that share through 2026 and 2027.

Does this affect Nvidia’s GPU business?

Not directly. Nvidia sells GPUs and platforms like DRIVE AGX Thor that pair with both Arm and x86 host CPUs, and Nvidia has shipped its own Arm-based Grace CPUs in past generations. The Arm-versus-x86 fight is mainly a battle between Arm, AMD, and Intel over the host CPU market, not the GPU accelerators Nvidia dominates.

Will x86 servers disappear?

The FTC opened a formal antitrust investigation on May 15, 2026 into whether Arm is using its licensing position to disadvantage companies like Apple, Qualcomm, and Nvidia, especially after Arm launched its own competing AGI data center CPU in March 2026. Qualcomm has also filed a separate lawsuit against Arm alleging breach of contract.

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Xeon 6+ “Clearwater Forest” is Intel’s first server chip built on its own 18A process node, with the flagship Xeon 6990E+ packing 288 efficiency cores. It’s a real technical milestone for Intel’s manufacturing comeback, but it launched on an older node generation than AMD’s 2nm Venice, and its real-world competitiveness against Arm’s efficiency numbers is still being tested in production deployments.

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

EPYC Venice is AMD’s sixth-generation server processor, and it’s the first high-performance computing chip in the industry to reach volume production on TSMC’s 2nm (N2) process node. The smaller node lets AMD more than double per-socket memory bandwidth to 1.6 TB/s and scale to 256 cores per socket.

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Custom silicon lets each cloud provider tune performance-per-watt and cost for its specific AI workloads rather than accept a general-purpose chip. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt are each built for the internal workloads of that specific cloud, which is why Google claims up to 2x performance-per-watt gains from Axion in its TPU hosts.

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

In rack-scale AI-accelerated server value, yes for Q1 2026: IDC data cited by Arm shows Arm-based servers at $53 billion versus x86’s $34.6 billion that quarter. In overall hyperscaler CPU compute share, Arm sits at roughly 50%, meaning x86 still accounts for the other half.

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Independent analysis is converging on the same direction even where the exact numbers differ. Next Platform’s July 30, 2026 review of IDC-sourced data concluded that “the headline shift is that non-x86 platforms were estimated at $58.7 billion in quarterly revenue, or 47.9% of the market,” a separate reading of the market that lands close to, though not identical to, Arm’s own Q1 2026 figures. That gap between two credible readings of similar underlying data is worth keeping in mind. The direction of the trend is well established, but the precise size of the lead depends on which quarter and which definition of “AI infrastructure spending” is used.

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Arm has been consistent in how it frames the shift to outside investors and the press. On its Q4 2026 earnings call, the company told analysts its first production data center silicon “will deliver more than 2x the performance per rack compared with x86 platforms with the potential to reduce AI data center capital expenditure by up to $10 billion per gigawatt,” according to the transcript published by The Globe and Mail.

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Wayve’s Gen 3 autonomous vehicle platform, running on Arm-powered Nvidia DRIVE AGX Thor hardware, has moved from testing to Transport for London-issued Private Hire Vehicle licenses for use with Uber, with more than 100,000 Londoners already signed up for early rides. Separately, Graphcore Research and Arm built Llama-Mobile, which compresses Meta’s Llama 3.2 Vision 11B model weights by more than 80% for Arm Neon hardware, and an Arm demo called First Contact runs a fine-tuned Gemma 3 1B model natively on Android for real-time game NPC conversations. None of that is server infrastructure, but it’s the same underlying bet: Arm’s power-efficiency profile fits where AI workloads are actually running in 2026, whether that’s a rack in a data center or a chip in someone’s pocket.

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

The server story is getting the headlines, but Arm’s August 2026 innovation recap shows the same architecture reaching further than data centers. Google’s new Pixel 11 lineup uses a Tensor G6 chip built on Arm CPU technology alongside Google’s own AI processing block, delivering 25% faster web browsing, 15% quicker app launches, and 50% more TPU compute than the prior generation. Gemini Nano tasks on-device reportedly run up to 3.5 times faster while using up to 3.5 times less energy, per Arm’s newsroom.

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Nvidia sits in an unusual spot too. Its DRIVE AGX Thor platform, used in Wayve’s Arm-powered autonomous vehicles now running supervised rides in London for Uber, is itself built on Arm cores, and Nvidia has shipped Arm-based Grace CPUs in past data center generations. Nvidia doesn’t need x86 to win for its GPU business to thrive, which is one reason the Arm-versus-x86 fight matters less to Nvidia’s bottom line than it does to Intel’s.

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

AMD is in a stronger position because it’s playing both sides. EPYC Venice keeps AMD’s x86 franchise competitive with a genuine 2nm-first claim, while the company’s Instinct GPU line and Helios rack-scale platform don’t care whether the host CPU next to them is x86 or Arm. That flexibility matters more as hyperscalers mix architectures within the same data center rather than standardizing on one.

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

For Intel, the stakes are existential in a way they haven’t been in decades. Losing half of hyperscaler CPU share to Arm while simultaneously trying to prove out its own 18A node in Clearwater Forest means Intel needs both its manufacturing bet and its architecture to work at the same time, with much less room for a stumble than it had five years ago.

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

What changed was the AI buildout itself. Training and inference workloads care less about legacy x86 software compatibility and more about performance-per-watt and per-rack economics, exactly the metrics Arm has built its 2026 pitch around. That’s why the climb from an estimated 18% hyperscaler share in mid-2024 to roughly 50% by mid-2026 happened during the same window that AI infrastructure spending itself exploded toward IDC’s $497 billion full-year 2026 forecast. The two trends aren’t a coincidence. They’re the same trend viewed from two angles.

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

x86 has been the default server architecture since Intel and AMD chips displaced proprietary RISC and mainframe systems through the 1990s and 2000s. Arm’s first real server attempt didn’t arrive until AWS launched its original Graviton chip in 2018, and for years afterward Arm servers were treated as a niche option for specific, cost-sensitive workloads rather than a general-purpose alternative.

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Qualcomm has filed a separate counter-lawsuit against Arm alleging breach of contract and interference with customer relationships. Neither the FTC probe nor the Qualcomm suit has stopped Arm’s licensing business day-to-day, but both add headline risk to the royalty structure underpinning Arm’s growth story. A regulator forcing changes to how Arm licenses its architecture to companies it now competes against would be one of the biggest threats to the momentum described above.

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Arm’s rise hasn’t gone unchallenged. The U.S. Federal Trade Commission opened a formal antitrust investigation into Arm Holdings on May 15, 2026, examining whether the company, which also launched its own competing AGI CPU for data centers in March 2026, is using its position to degrade or deny the architecture licenses that Apple, Qualcomm, Nvidia, and hundreds of other companies depend on, per Tech Times.

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Those workload types matter because they’re the backbone of retrieval-augmented generation and agentic AI pipelines, where a system repeatedly searches, retrieves context, and acts on the result. Lower tail latency at the retrieval step compounds across a multi-step agent chain, so a 30-50% latency cut at the database layer can translate into a noticeably faster end-to-end agent response, not just a faster search query in isolation.

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Beyond the market-share numbers, Arm and Elastic published head-to-head benchmark data that gives the shift some concrete engineering backing. Testing Elasticsearch on Arm Neoverse-based AWS Graviton5 processors showed up to 48% higher throughput and between 31.7% and 53.8% lower P99 latency compared with the tested Intel Xeon 6 configurations, across representative geospatial, observability, and document-retrieval workloads, according to Arm’s own newsroom writeup.

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

This is the quiet variable in the Arm-versus-x86 story. Arm’s own designs (Graviton, Axion, Cobalt) are fabbed by the hyperscalers’ chosen foundry partners under long-term wafer agreements, while AMD’s newest, highest-bandwidth EPYC chip is fighting Apple and three other major customers for the same limited pool of leading-edge wafers. If 2nm capacity stays tight through 2027, that alone could shape how fast x86 can close the gap Arm has opened.

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

AMD’s Venice doesn’t get to scale in a vacuum. Apple has secured roughly half of TSMC’s available 2nm output for its iPhone 18 A20 processor and its own M-series chips, and AMD is sharing what’s left of that N2 capacity with Qualcomm, Nvidia, and MediaTek. Hyperscaler procurement teams were reportedly tracking 2nm wafer allocation closely during Computex week, because for Venice, supply rather than spec sheet may end up deciding which buyers get chips first.

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

For Intel, Clearwater Forest carries weight beyond its own spec sheet. It’s the company’s first server chip built on a node it manufactures itself at that leading edge, after years of leaning on TSMC for its most advanced designs. Whether 18A yields hold up at volume, and whether hyperscalers actually design Clearwater Forest into new AI clusters at scale, will say more about Intel’s data center comeback than the launch event itself did.

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Intel’s response landed on the same Computex 2026 stage. The Xeon 6+ family, codenamed Clearwater Forest, formally launched that week, putting Intel’s 18A process node into shipping server hardware for the first time. The flagship Xeon 6990E+ packs 288 Darkmont efficiency cores onto a single chip, per Tech Times’ reporting.

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

AMD’s Helios rack-scale platform pairs Venice CPUs with Instinct MI450X GPUs and is targeting multi-gigawatt deployments in the second half of 2026. A follow-on chip codenamed Verano, also built on 2nm, is already in development and tuned specifically for agentic AI workloads through native LPDDR memory support, a sign AMD expects the agentic-AI memory profile to matter enough to design around.

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

The specs represent a real generational jump rather than an incremental refresh. Per-socket memory bandwidth more than doubles to 1.6 TB/s, up from 614 GB/s on the prior generation, while CPU-to-GPU bandwidth gets a 2x boost. The flagship configuration scales to 256 cores per socket, with AMD claiming roughly a 70% performance improvement over the prior EPYC generation. AMD CEO Lisa Su called ramping Venice on TSMC’s 2nm process “an important step forward in accelerating the next generation of AI infrastructure,” a statement Tech Times reported from the Computex floor.

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

AMD isn’t ceding the data center without a fight. At Computex 2026, the company confirmed its sixth-generation EPYC server processor, codenamed Venice, had entered full-scale volume production on TSMC’s 2nm process node, the first high-performance computing product in the industry to reach that node, according to Tech Times.

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

This is the part of the story that separates the current Arm push from prior attempts to dent x86’s server dominance. AWS shipped its first Graviton chip back in 2018 and spent years proving the architecture could handle general workloads. What’s different in 2026 is that Google, Amazon, and Microsoft are simultaneously running Arm silicon at production scale for AI-specific workloads, not just general compute, and doing it with chips they designed themselves rather than chips bought off a vendor’s shelf.

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Amazon’s custom silicon portfolio, spanning Arm-based Graviton CPUs, Trainium AI accelerators, and Nitro networking chips, has crossed a $20 billion annual revenue run rate and is still growing at triple-digit percentage rates year-over-year. Microsoft’s Arm-based Cobalt CPUs, meanwhile, have moved past pilot status and are now running production workloads across multiple Azure regions for enterprise customers including Databricks, Siemens, and Snowflake.

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

None of the big three cloud providers are waiting for Arm to hand them a reference design. Each has its own custom Arm-based CPU program running in production. Google’s next-generation TPU pods are dropping x86 host processors in favor of custom Arm-based Axion chips, with Google claiming up to 2x better performance-per-watt versus the prior x86-based generation. The company also says its TPU 8t delivers 2.7x better training performance-per-dollar and its TPU 8i delivers 80% better inference performance-per-dollar, figures reported by Tech Times from Computex 2026.

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Arm’s earnings call transcript makes the capital-expenditure pitch even more explicit. Arm told investors its first production silicon product for the data center “will deliver more than 2x the performance per rack compared with x86 platforms with the potential to reduce AI data center capital expenditure by up to $10 billion per gigawatt,” per the Q4 2026 earnings call transcript published by The Globe and Mail. For hyperscalers now building AI campuses measured in gigawatts, that kind of per-gigawatt savings claim, even before it’s independently verified, is enough to justify a serious pilot.

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Arm has also argued the decision criteria have broadened past raw clock speed. As the company put it in a separate newsroom post, “rather than focusing only on CPU peak performance, AI infrastructure decisions increasingly depend on system-level efficiency, accelerator utilization, power consumption, software portability, and total cost of ownership,” according to Arm’s own newsroom. That framing matters because it’s an admission that Arm doesn’t need to beat x86 on every spec sheet metric. It needs to win on power draw per rack and dollars per training run, and those are the numbers hyperscalers actually budget against.

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Arm frames the shift as a change in what buyers optimize for. In a company newsroom post, Arm stated that “agentic AI requires a new type of data center infrastructure, and the CPU is central to this,” a line the company has repeated across its Hot Chips 2026 presentation and its own blog coverage of converged AI data center architecture.

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Put together, the trend line is consistent across two independent citations of IDC’s work even though the exact quarters and definitions differ slightly. x86 revenue in AI-accelerated infrastructure keeps shrinking as a share of a market that itself keeps growing.

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

That $34.6 billion x86 figure is the tail end of a slide. Earlier Arm citations of the same IDC dataset show x86 accelerated server value falling from $51.9 billion in the third quarter of 2025 to $42.7 billion in the fourth quarter, then to $34.6 billion in the first quarter of 2026, a three-quarter drop of more than $17 billion. A separate July 30, 2026 analysis on Next Platform, drawing on its own read of IDC-sourced figures, put non-x86 platforms at $58.7 billion in quarterly revenue, or 47.9% of the market, in a later snapshot using a different quarter and methodology than Arm’s Q1 number, but pointing the same direction.

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Arm’s September 1 newsroom recap cites IDC data putting global AI infrastructure spending at $89.7 billion in the first quarter of 2026 alone. Within that quarter, Arm-based rack-scale GPU server value reached $53 billion, versus $34.6 billion for x86. IDC has since raised its full-year 2026 forecast for AI infrastructure spending to $497 billion.

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

The IDC Numbers Behind the Shift

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Every major cloud operator has a piece of this story. Google is swapping x86 host processors in its next-generation TPU pods for custom Arm-based Axion CPUs. Amazon’s custom silicon line, which spans Arm-based Graviton chips alongside Trainium AI accelerators and Nitro networking silicon, has crossed a $20 billion annual revenue run rate and keeps growing at triple-digit rates year-over-year. Microsoft’s Arm-based Cobalt CPUs are now running production workloads across Azure regions for customers including Databricks, Siemens, and Snowflake.

The IDC Numbers Behind the Shift

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Arm’s own fiscal 2026 results back up the trend. The company posted record full-year revenue of $4.92 billion, and data center royalties more than doubled year-over-year for the second consecutive year. That’s not a one-quarter blip. Royalty growth compounding at that rate for two straight years points to hyperscalers locking in multi-year Arm commitments rather than just testing the waters.

The IDC Numbers Behind the Shift

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

The headline number is simple: Arm now accounts for roughly half of CPU compute deployed by the world’s top cloud operators. Tech Times pegs the starting point at about 18% in mid-2024, with the climb to 50% compressing into roughly two years and lining up almost exactly with the industry’s pivot toward AI infrastructure spending.

The IDC Numbers Behind the Shift

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

The IDC Numbers Behind the Shift

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

The shift didn’t happen overnight, but it happened fast. Arm’s compute share among the largest hyperscalers sat at roughly 18% in mid-2024. By mid-2026 it had climbed to around 50%, according to Tech Times reporting from Computex 2026. That’s a two-year run that reset how Google, Amazon, and Microsoft buy compute, and it’s pushing AMD and Intel toward their biggest architectural bets in years.

The IDC Numbers Behind the Shift

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Arm-based server chips have pulled ahead of x86 in a market x86 owned for four decades. New data cited by Arm’s own newsroom on September 1, 2026 shows Arm-based rack-scale GPU server value hit $53 billion in the first quarter of 2026, ahead of x86’s $34.6 billion, inside an $89.7 billion quarter for global AI infrastructure spending. IDC now expects that full-year AI infrastructure spending to reach $497 billion in 2026.

The IDC Numbers Behind the Shift

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

The IDC Numbers Behind the Shift

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

The IDC Numbers Behind the Shift

Period	x86 Accelerated Server Value	Arm / Non-x86 Value	Source
Q3 2025	$51.9B	N/A	IDC data cited by Arm
Q4 2025	$42.7B	N/A	IDC data cited by Arm
Q1 2026	$34.6B	$53B (Arm rack-scale GPU servers)	IDC via Arm newsroom, Sept. 1, 2026
Later 2026 snapshot	N/A	$58.7B / 47.9% share (non-x86)	Next Platform, July 30, 2026
Full-year 2026 forecast	N/A	$497B total AI infrastructure spend	IDC via Arm newsroom

Why Hyperscalers Are Defaulting to Arm

Google, AWS, and Microsoft Are All Building Custom Arm Silicon

AMD’s Answer: EPYC Venice Hits Volume Production on TSMC’s 2nm Node

Intel Fights Back With Xeon 6+ “Clearwater Forest” on 18A

The TSMC 2nm Capacity Squeeze Nobody Can Escape

Performance Data Point: Graviton5 Beats Intel Xeon 6 by Up to 48%

Regulatory Risk: The FTC Is Investigating Arm Holdings

Historical Context: x86 Ruled Servers for Four Decades

Arm vs x86: Head-to-Head Comparison

The table below pulls together the verified specs and figures from Arm, AMD, Intel, and the Arm/Elastic benchmark data cited above.

Metric	Arm (Graviton5 / Axion / Cobalt)	x86 (AMD EPYC Venice / Intel Xeon 6+)
Hyperscaler CPU compute share (2026)	~50%	~50% (combined AMD + Intel)
Leading-edge process node	Varies by hyperscaler design	2nm TSMC N2 (AMD Venice), Intel 18A (Xeon 6+)
Max cores per socket	Not disclosed at this detail	256 (EPYC Venice), 288 Darkmont efficiency cores (Xeon 6990E+)
Per-socket memory bandwidth	Not disclosed at this detail	1.6 TB/s (Venice, up from 614 GB/s prior gen)
Elasticsearch throughput vs. Xeon 6 baseline	Up to 48% higher (Graviton5)	Baseline
Elasticsearch P99 latency vs. Xeon 6 baseline	31.7%-53.8% lower (Graviton5)	Baseline
TPU host CPU performance-per-watt gain	Up to 2x (Axion vs. prior x86-based TPU host)	N/A
Custom-silicon annual revenue run rate	$20B+ (AWS: Graviton + Trainium + Nitro)	Not broken out separately

Market Impact: What This Means for Intel, AMD, and Nvidia

Beyond the Data Center: Arm’s Reach Into Mobile, Robotics, and Autonomous Vehicles

What Industry Voices Are Saying

Predictions: Where the Arm vs x86 Battle Goes Next

x86’s share keeps shrinking through 2027, but doesn’t collapse. AMD’s Venice and Intel’s Clearwater Forest give x86 real answers on bandwidth and core count, enough to hold a meaningful floor even as Arm’s share climbs past 50%.
The FTC investigation becomes the swing factor for Arm’s royalty model. If regulators force licensing changes, Arm’s data center momentum could slow regardless of how good its chips are.
2nm wafer allocation, not chip design, decides AMD’s near-term ceiling. With Apple holding roughly half of TSMC’s 2nm output, AMD’s ability to ship Venice at volume depends as much on foundry capacity as on demand.
More hyperscalers will custom-design their own Arm silicon rather than buy off-the-shelf. Google’s Axion, AWS’s Graviton, and Microsoft’s Cobalt set a pattern smaller cloud providers will likely try to copy or license.
Agentic AI workloads push memory bandwidth, not raw core count, to the top of the spec sheet. Both AMD’s LPDDR-equipped Verano and Arm’s system-level efficiency pitch point toward the same conclusion: the next fight is about memory and power, not clock speed.

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

Arm vs x86 in AI Servers: $53B Beats $34.6B [2026]

Will x86 servers disappear?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Predictions: Where the Arm vs x86 Battle Goes Next

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?

What is the FTC investigating Arm Holdings for?

Does this affect Nvidia’s GPU business?

Will x86 servers disappear?

Predictions: Where the Arm vs x86 Battle Goes Next

Frequently Asked Questions

Has Arm actually overtaken x86 in the data center?

Why are Google, AWS, and Microsoft building their own Arm chips instead of buying from Intel or AMD?

What is AMD’s EPYC Venice and why does the 2nm node matter?

Is Intel’s Xeon 6+ competitive with Arm and AMD’s newest chips?