AMD CEO Lisa Su spent October 6 and 7 on a two-city tour that amounted to a public warning: the company cannot build AI chips fast enough. In Taipei on October 6, 2026, Su told reporters that demand for AMD’s AI-related silicon, spanning GPUs, CPUs, memory, and advanced packaging, is running ahead of what the supply chain can produce, according to a Reuters report republished by Yahoo Finance. A day later, in Seoul, she was courting South Korean chipmakers to help plug the gap. In between, market reporting pointed to AMD’s next-generation EPYC Venice server CPU as the clearest symptom: booked through 2027, with some orders reportedly pushed into 2028.
None of this is AMD announcing a new product. It is AMD’s chief executive, on consecutive days, in two different countries, telling anyone listening that the AI buildout has outrun the factories building it. That is a different kind of story than a launch event, and it carries different implications for anyone tracking AMD EPYC Venice, AMD’s stock, or the broader AI hardware supply chain heading into 2027.
What Lisa Su Actually Told Reporters in Taipei
Su’s Taipei stop was about supply chain logistics, not marketing. According to Reuters’ October 6, 2026 report, she said AMD had already increased supply through 2026 and plans to substantially increase it again in 2027, while adding the company “can definitely use more.” She also described demand as holding at a very high level for several years, which is why AMD needs additional advanced wafer capacity.
Su has been saying variations of this for months. Back in a February 4, 2026 interview on CNBC’s Squawk on the Street, discussing AMD’s AI demand guidance, she put it plainly:
“What I would tell you from someone on the inside is AI is accelerating at a pace that I would not have imagined.”
Lisa Su, Chair and CEO, AMD — CNBC, February 4, 2026
Eight months later, the Taipei comments read like a continuation of that thought, except now the gap between demand and supply is wide enough that AMD felt compelled to fly its CEO to the island that makes most of its chips and say so out loud.
EPYC Venice Bookings Reportedly Stretch Into 2028
The sharpest data point tied to Su’s remarks involves AMD EPYC Venice, the company’s upcoming server CPU line. A report published October 6 and updated October 7, 2026 by market-intelligence site PrimeXBT said EPYC Venice capacity was effectively sold out through 2027, with additional orders being pushed into 2028.
That claim deserves a caveat. It is reported market intelligence, not a formally disclosed AMD backlog figure. AMD has not published a Venice unit count, named the customers behind the bookings, or attached a dollar value to the backlog. What AMD has confirmed, through Su’s own remarks, is the broader picture: supply increased in 2026, will increase substantially again in 2027, and still will not fully satisfy demand.
Separately, Taiwan News reported on October 6, updated October 7, that Venice has entered mass production on TSMC’s 2-nanometer-class process and is expected to reach broad availability in 2027. That, too, is attributed to market sources rather than a detailed AMD technical disclosure, so treat the node and timing as reported rather than confirmed. AMD has previously demonstrated Venice’s early performance edge in internal benchmarking, a milestone covered in detail when AMD claimed EPYC Venice beat Intel Xeon by 2.37x and edged out Nvidia’s own CPU design. What was missing from that earlier benchmark disclosure, and is still missing now, is a confirmed core count, chiplet configuration, or cache layout for the chip.
AMD Moves to a Three-to-Five-Year Supply Planning Horizon
The more structurally important line from Taipei was about planning horizons, not products. Seoul Economic Daily’s October 7, 2026 report said Su described AMD as shifting its supply-chain planning from roughly one to two years ahead to three to five years ahead. Reuters’ Taipei coverage framed the same shift as a response to demand that AMD now expects to stay elevated for years rather than quarters.
That is a meaningful operational change. Locking in wafer allocations, packaging slots, and substrate capacity three to five years out means AMD is making multi-billion-dollar capital commitments against demand it cannot yet fully quantify. It also means AMD’s foundry partners, led by TSMC, are being asked to commit capacity further into the future than the industry’s historical norm, at a moment when TSMC itself is already weighing a Texas fab to supplement its $265 billion Arizona buildout.
Where the Actual Bottleneck Sits: Wafers, HBM, and Packaging
Su’s comments, and the coverage around them, point to a constraint that runs wider than any single chip. Taiwan News and Yahoo Finance both described the pinch points as advanced logic wafers, high-bandwidth memory, advanced packaging, substrates, and testing capacity, essentially every step between a finished wafer and a chip that can sit inside a server.
That lines up with what has already been playing out across the AI hardware market this year. HBM has been the recurring choke point: Nvidia’s own next-generation Rubin Ultra accelerator has reportedly lost roughly a third of its intended memory capacity to the HBM shortage, and memory maker Micron posted record revenue of $54.2 billion while explicitly flagging that it is tightening memory supply, not loosening it. If Su’s framing is accurate, AMD is now describing the same memory and packaging crunch that has already dented plans at Nvidia, just from the CPU side of the rack instead of the GPU side.
The Seoul Roundtable: AMD Courts South Korea’s Sovereign AI Push
On October 7, 2026, Su moved from Taipei to Seoul for a second round of meetings, this time with South Korean government officials and chipmakers. According to South Korea’s Ministry of Science and ICT, as reported by SBS News, Second Vice Minister Ryu Je-myung met Su at the Four Seasons Hotel Seoul, followed by a roundtable involving 14 South Korean AI-semiconductor companies.
Outlets Asiae, Aju Press, and Digital Today each covered the session with a similar framing: the goal is an open, heterogeneous AI ecosystem that pairs AMD CPUs and GPUs with domestic South Korean neural processing units, in support of the country’s sovereign-AI infrastructure ambitions. Reported discussion points included integrating Korean NPUs with AMD silicon, cooperation among Korean AI-chip startups and AMD, and a general preference for heterogeneous computing over a single-vendor hardware stack.
The timing is not subtle. A CEO who just told Taiwan that her company cannot produce enough chips spent the very next day in Seoul lining up more places to build demand, and implicitly, more partners who might help absorb some of the capacity crunch through alternative, non-AMD silicon working alongside AMD’s own CPUs and GPUs.
“There’s very, very high demand for the next several years.”
Lisa Su, Chair and CEO, AMD — Yahoo Finance, October 6, 2026
EPYC Genoa to Turin to Venice: AMD’s Server Chip Ladder
Venice did not appear out of nowhere. It is the next rung on a naming ladder AMD has climbed through several server CPU generations, each tied to a new Zen core architecture and, generally, a newer TSMC manufacturing node.
EPYC Genoa
EPYC Genoa was AMD’s fourth-generation EPYC family, built on the Zen 4 architecture and introduced for the 2022-2023 server cycle. It established the chiplet pattern AMD has stuck with since: multiple compute dies paired with a separate input-output die, a design that let AMD scale core counts without redesigning the whole chip for every generation.
EPYC Turin
EPYC Turin followed as the fifth-generation platform, built principally around Zen 5 and introduced during the 2024-2025 period. It is the generation currently shipping in volume into data centers and is the direct predecessor to Venice.
EPYC Venice
EPYC Venice is the generation now at the center of the shortage story. It is reportedly targeting a newer TSMC process, expected general availability in 2027, and, per the market reports described above, demand that has already pushed some bookings into 2028 before the chip has even shipped widely. AMD has not publicly disclosed Venice’s exact core count, chiplet layout, or cache configuration as of October 7, 2026, so any such figures circulating online should be treated as unconfirmed until AMD says otherwise.
How This Compares to Nvidia and Intel’s Supply Pictures
It would be convenient to say AMD’s shortage is worse, or better, than what Nvidia and Intel are each dealing with. The available reporting from October 6-7 does not actually support that comparison. There is no verified Nvidia backlog figure or Nvidia executive statement from the same window, and no directly comparable Intel capacity disclosure either.
What the reporting does support is that this is a system-wide constraint, not an AMD-specific failure. Nvidia’s Rubin Ultra has already absorbed an HBM-driven memory cut, as covered above, and the memory shortage generally has forced tradeoffs across the industry. Intel’s own supply position carries a different structural wrinkle: Intel CEO Lip-Bu Tan said earlier this year that memory prices had risen roughly sevenfold with no relief expected until 2028, almost the same year AMD’s Venice bookings are reportedly spilling into. The difference is architectural more than competitive: Intel still runs significant internal fabs, while AMD depends almost entirely on external foundries, chiefly TSMC, for leading-edge logic, which makes AMD’s supply story a direct proxy for TSMC’s allocation decisions.
Market Impact: Why a CPU Shortage Ripples Through the Whole AI Buildout
The instinct is to treat GPUs as the AI supply story and CPUs as an afterthought. That instinct is wrong, and AMD’s own system design suggests otherwise. Seoul Economic Daily’s reporting on AMD’s Helios rack architecture described a configuration pairing 18 Venice CPUs with 72 Instinct MI455X GPUs, a reported system configuration rather than a confirmed architectural spec, but directionally consistent with how modern AI racks work: GPUs do the training and inference math, but CPUs handle orchestration, networking, and data movement across the rack. A shortage on the CPU side can throttle how fast a data center comes fully online even if every GPU it needs is sitting in a warehouse.
That matters for AMD’s own market story. The company crossed a trillion dollars in market capitalization this year on the strength of AI-driven investor enthusiasm, a run detailed when AMD’s stock jumped 9.6% to cross that threshold. A CEO-confirmed demand-exceeds-supply signal reinforces the bull case for revenue growth, but it simultaneously flags execution risk: if Venice bookings really are spilling into 2028, some hyperscaler deployments that were modeled around 2027 availability may need to slip, which is a very different outcome for AMD’s near-term guidance than for its long-term growth story. For broader context on where this fits, see our ongoing hardware coverage.
AMD’s Supply Timeline: October 6-7, 2026 at a Glance
| Date | Location | Event or Statement | Source |
|---|---|---|---|
| Oct. 6, 2026 | Taipei | Su says demand outpaces supply; AMD to substantially increase 2027 supply | Reuters, via Yahoo Finance |
| Oct. 6, 2026 | Taipei | AMD seeks expanded capacity from TSMC and packaging, testing, substrate partners | Taiwan News |
| Oct. 6-7, 2026 | Market reports | EPYC Venice reportedly booked through 2027, orders pushed into 2028 (unconfirmed detail) | PrimeXBT |
| Oct. 7, 2026 | Seoul | Su meets Second Vice Minister Ryu Je-myung at Four Seasons Hotel Seoul | SBS News |
| Oct. 7, 2026 | Seoul | Roundtable with 14 South Korean AI-semiconductor companies on open ecosystem cooperation | Asiae, Aju Press, Digital Today |
| Feb. 4, 2026 | CNBC interview | Su says AI is accelerating faster than she imagined | CNBC |
EPYC Server CPU Generations Compared
| Generation | Core Architecture | Reported Node | Launch Era | Status as of Oct. 7, 2026 |
|---|---|---|---|---|
| EPYC Genoa | Zen 4 | TSMC advanced node (4th-gen EPYC) | 2022-2023 | Prior generation, widely deployed |
| EPYC Turin | Zen 5 (primary) | TSMC advanced node (5th-gen EPYC) | 2024-2025 | Current shipping generation |
| EPYC Venice | Next-gen Zen (unconfirmed by AMD) | Reported TSMC 2nm-class | Targeted 2027 | Reportedly booked through 2027, orders reported into 2028; core count unconfirmed |
Treat the Venice row as the most provisional of the three. AMD has confirmed the chip exists and has shown early comparative benchmarks, but has not published a technical spec sheet, making every number attached to its node, core count, or cache configuration a reported estimate rather than an AMD-confirmed fact.
Five Predictions for AMD’s Chip Supply Through 2028
- AMD will likely be pressed to disclose firmer EPYC Venice specifications, including core count and socket configuration, at a dedicated product event ahead of its targeted 2027 availability, simply because the gap between reported demand and official technical detail has grown too wide to ignore.
- Expect AMD to sign additional regional partnerships modeled on the Seoul roundtable, most plausibly in Europe, India, or the Middle East, as governments pursue their own sovereign-AI infrastructure and AMD looks to diversify where its constrained supply gets allocated.
- The shift to a three-to-five-year planning horizon will likely translate into more multi-year capacity agreements with TSMC and packaging or substrate partners, a pattern already visible in the broader fab-expansion debate playing out around TSMC’s prospective Texas site.
- If EPYC Venice bookings really do extend into 2028, some hyperscaler AI rack deployments pairing Venice CPUs with next-generation Instinct GPUs will likely slip from originally modeled 2027 timelines, even if GPU-side supply improves independently.
- AMD’s stock is likely to stay sensitive to every supply-chain comment from Su for the rest of this cycle. Investors have already rewarded the stock for AI demand once this year. Any sign that supply cannot keep pace could cut both ways, reinforcing the growth story while raising execution-risk concerns.
Historical Context: A Pattern AMD Has Lived Through Before
AMD has spent the better part of three years riding, and occasionally getting caught behind, the same demand curve. Each EPYC generation since Genoa has arrived into a market hungrier than the one before it, and each has leaned harder on TSMC’s leading-edge capacity than the last. What is different this time is the explicitness of the warning. Su is not describing a temporary parts shortage or a one-quarter supply hiccup. She is describing a multi-year structural mismatch that has already forced AMD to triple its planning horizon, from one to two years out to three to five. That is the language of a company bracing for sustained scarcity, not managing a short-term bottleneck.
Frequently Asked Questions
What exactly did AMD’s Lisa Su say about AI chip demand?
Speaking to reporters in Taipei on October 6, 2026, Su said AMD’s demand for AI-related chips, including GPUs, CPUs, memory, and packaging, exceeds what the company can currently supply, and that AMD plans a substantial supply increase in 2027 while expecting very high demand to persist for several years, according to Reuters.
What is AMD EPYC Venice?
EPYC Venice is AMD’s next-generation server CPU, following EPYC Turin. It is reportedly built on a newer TSMC process and targeted for broad availability in 2027, though AMD has not published a full technical specification.
Is EPYC Venice actually sold out?
Market-intelligence site PrimeXBT reported on October 6, updated October 7, 2026, that Venice capacity was booked through 2027 with some orders pushed into 2028. That figure has not been confirmed by AMD as an official backlog number, so it should be treated as reported rather than verified.
Why is AMD meeting with South Korean officials?
On October 7, 2026, Su met South Korea’s Ministry of Science and ICT and held a roundtable with 14 domestic AI-semiconductor companies to discuss an open, heterogeneous AI ecosystem that integrates Korean NPUs with AMD CPUs and GPUs, supporting South Korea’s sovereign-AI infrastructure plans.
Is this shortage specific to AMD, or industry-wide?
Reporting points to a system-wide constraint across advanced wafers, high-bandwidth memory, packaging, and substrates, affecting AI hardware broadly. Nvidia’s Rubin Ultra accelerator has separately lost memory capacity to the HBM shortage, suggesting the bottleneck is not unique to AMD.
When will EPYC Venice actually ship in volume?
Taiwan News reported Venice has entered mass production with broad availability expected in 2027, though that timing comes from market sources rather than an AMD product announcement.
How does this affect Nvidia and Intel?
There is no verified, directly comparable Nvidia or Intel backlog figure from the same October 6-7 window. The broader supply constraints in memory and packaging are known to affect Nvidia’s Rubin Ultra plans, while Intel has separately warned of memory price increases persisting until 2028.
Could this delay AI data center buildouts?
It is a real risk. AMD’s Helios rack design reportedly pairs Venice CPUs with Instinct GPUs in the same system, so a CPU-side supply constraint could slow full-rack deployments even if GPU supply improves on its own timeline.
Related
- AMD EPYC Venice Beats Xeon 2.37x, Edges Nvidia CPU [2026]
- Rubin Ultra Loses 33% of Its Memory to HBM Shortage [2026]
- Micron Posts Record $54.2B, Tightens Memory Supply [2026]
- TSMC Weighs Texas Fab Beyond $265B Arizona Bet [2026]
- AMD Hits $1 Trillion Market Cap After 9.6% Surge [2026]
