Google used its annual Research@ event in Mountain View, California, on October 14, 2026, to preview a new low-power AI chip built with Synaptics, setting up a formal unveiling at Synaptics’ Tech Day in San Jose on October 20. The chip pairs Google’s Coral NPU M2 with Synaptics’ Torq NPU and Arm CPU cores, and the companies say it cuts energy use by 40% compared with existing edge AI processors. Synaptics CEO Rahul Patel said the chip will not stay confined to lab demos. According to a report from R&D World, Patel told attendees it will also be built into Google devices, though neither company named which products or when they would ship.
The preview lands at a moment when chipmakers are racing to put AI inference directly on wearables, smart glasses, and industrial sensors instead of routing every request to the cloud. Google and Synaptics are betting that sub-6-milliwatt inference, paired with an open compiler stack, can pull developers away from the proprietary microcontroller software they have relied on for years. The timing also puts pressure on rivals already shipping edge AI silicon at scale, from Qualcomm’s Snapdragon line to smaller microcontroller specialists like Ambiq, NXP, and STMicroelectronics.
What Google and Synaptics Revealed at Research@
Google Research’s Research@ event is the company’s internal showcase for work still moving from lab to product, and this year’s edition gave Synaptics a stage to describe a chip that had been in development for roughly 18 to 24 months. The device belongs to Synaptics’ Astra line of AI-native processors and microcontrollers, a product family the company has built specifically for local, low-power AI workloads rather than general-purpose computing.
Patel used the Mountain View appearance to lay out the chip’s capabilities without disclosing full specifications, a sequencing choice that let Google tie the story to its broader research narrative before Synaptics controls the commercial unveiling six days later. The chip can process voice, vision, motion, and contextual sensing data simultaneously, and it adds GPU and multimedia processing along with hardware-rooted security, according to the companies’ public statements cited in a report from SBS.
Inside the Coral NPU M2 and Its 40% Power Claim
The headline number from the preview is a claimed 40% cut in energy use for Google’s Coral NPU M2, the successor to the Coral neural processing unit Google introduced the prior year. Reporting tied to the announcement, including coverage from ChosunBiz, describes M2 running on-device inference at an average power draw of less than 6 milliwatts. Neither Google nor Synaptics has specified the exact workloads used for that comparison, or which prior-generation processor served as the baseline, so the 40% figure should be read as a vendor claim rather than an independently benchmarked result.
That caveat matters because power-efficiency claims in the chip industry are notoriously workload-dependent. A processor that looks dramatically more efficient on a simple keyword-spotting task can lose much of its edge on continuous multimodal sensing, which is exactly the use case Google and Synaptics are targeting. Until Synaptics publishes a full datasheet, outside engineers will not be able to verify the 40% number against a defined test suite.
Reported M2 inference draw: < 6 mW
Reported efficiency claim: 40% less energy vs. prior-generation processors
Comparison baseline disclosed: No (workload and reference chip not specified)
Full-chip TOPS rating disclosed: NoThe Astra Platform: Torq NPU Meets Arm Cores
Synaptics did not simply license Google’s silicon design and ship it unchanged. The Astra chip combines the Coral NPU M2 with Synaptics’ own Torq NPU and standard Arm CPU cores, giving the company a path to differentiate on top of Google’s open accelerator work. That architecture lets Synaptics target a wide span of constrained devices, from battery-powered wearables to fixed industrial cameras, with one underlying platform rather than a separate chip for each category.
An Open Compiler Stack Built on MLIR
A less flashy but arguably more consequential part of the announcement is software. Synaptics and Google Research spent roughly 18 months building an open-source compiler on top of MLIR, the Multi-Level Intermediate Representation framework, so the chip can run standard machine learning frameworks and model formats rather than locking developers into a proprietary toolchain. Patel framed this as a break from the walled-garden software that has defined microcontroller development for years, a point echoed in R&D World’s account of his remarks. Developers can already prototype against the underlying Coral NPU using Coralboard, a development platform Synaptics launched earlier this year that pairs the NPU with Astra processors ahead of the full chip’s release.
RISC-V Roots and the Road to Coral NPU M3
Coral’s first milestone was a front end built on RISC-V, the open instruction set architecture that has gained ground across the chip industry as an alternative to proprietary cores. M2 marks the second milestone and adds what Google describes as the first Coral vector processor. Google Research has also said its next design, M3, is already complete and adds native 32-bit floating-point support so the chip can run Gemma 3 270M, a compact 270-million-parameter language model, directly on-device. Neither company has given a shipping date for M3-based silicon, which means the chip debuting this month is already one generation behind Google’s internal roadmap.
Rahul Patel’s Pitch: From Lab Bench to Google Hardware
Patel’s most direct claim from the Research@ appearance was that the chip will not stay in the lab and will also be built into Google devices, a statement widely picked up across outlets covering the preview. He also highlighted the microcontroller’s support for high-density DRAM, describing memory capacity as a source of scalability for future products built on the same platform. Synaptics plans to formally unveil the chip at its Tech Day event on October 20 at 1151 McKay Drive in San Jose, which the company has billed as including a noon press and analyst briefing followed by a demonstration showcase.
What Patel did not say is just as notable. He declined to identify which Google hardware lines would adopt the chip or offer any release window, leaving a gap between the marketing claim and a verifiable product commitment. That gap is where skepticism from hardware analysts tends to concentrate, since chipmakers routinely tout future design wins that take years, or never materialize, to reach shelves.
Why Google Keeps Investing in Edge Silicon Partnerships
Google’s data center strategy has long rested on designing its own Tensor Processing Units alongside the models that run on them, and the company is now pushing the same co-design philosophy to the edge. The logic, as described in reporting on the Research@ event, is that existing edge chips consume too much energy and respond too slowly for always-on, ambient AI experiences that keep personal data on the device instead of sending it to the cloud. A fragmented market of proprietary microcontroller designs compounds the problem by making it harder for developers to build once and deploy across multiple vendors’ hardware.
That framing explains why Google chose a partnership model rather than building its own edge chip from scratch. Synaptics brings decades of microcontroller and sensor-fusion experience along with existing customer relationships in wearables and industrial equipment, while Google supplies the Coral accelerator design and compiler work it has already validated internally.
Billy Rutledge Makes the Case for Co-Designed Hardware
When Google and Synaptics first announced their collaboration on edge AI for the Internet of Things, Billy Rutledge, Director of Systems Research at Google Research, laid out why the two companies paired up in the first place. “Synaptics’ embrace of open software and tools and proven AI hardware makes the Astra portfolio a natural fit for our ML core as we ramp to meet the uniquely challenging power, performance, cost, and space requirements of Edge AI devices,” Rutledge said in the companies’ joint statement announcing the partnership.
Rutledge closed that announcement with a line that reads differently now that the chip has reached a public preview. “We look forward to working together to bring our capabilities to the broad market,” he said. Nearly two years of engineering separate that statement from this month’s Research@ demonstration, which is roughly in line with the 18-to-24-month development window Patel cited for the project.
Patrick Mannion Explains What Astra Actually Adds
Synaptics spokesperson Patrick Mannion gave the clearest public explanation of the division of labor between Google’s open core and Synaptics’ own hardware in remarks made around CES 2025. “What we’re doing is taking their open ML core and adding our own hardware engine as an enhancement,” Mannion said. He added that the goal was tuning that shared foundation for the specific operators Synaptics’ engine supports: “We’re making that open core run better for the set of operators that we support in the engine.”
Mannion also confirmed the architectural lineage underpinning the whole platform in a brief, direct answer about the subsystem’s design. “It’s RISC-V-based,” he said, a detail that lines up with Google’s own description of Coral’s first milestone as a RISC-V front end before M2 added the vector processor on top of it.
Target Devices: Wearables, Smart Glasses, and the Industrial Floor
The use cases Google and Synaptics are chasing span two very different markets. On the consumer side, smart glasses, watches, and connected cameras need to recognize speech, gestures, and context without draining a small battery in a few hours. On the industrial side, vision and voice systems on factory floors need similar always-on sensing but with tighter requirements around reliability and hardware-rooted security, since these devices often sit on networks that also touch safety-critical equipment.
Covering both markets with one chip platform is an ambitious bet. It means Synaptics has to hit aggressive power targets for battery-powered wearables while also meeting the durability and security expectations of industrial buyers, all on the same underlying silicon. If the company pulls it off, Astra could become a default reference design that OEMs reach for instead of commissioning custom edge AI silicon.
A Decade of Google’s Edge AI Bets
This announcement did not come out of nowhere. Google’s interest in specialized AI silicon traces back to a 2017 Google research paper on its first-generation Tensor Processing Unit, which reported performance-per-watt gains of 30 to 80 times over the Intel Haswell CPUs and Nvidia K80 GPUs it was benchmarked against in production neural-network inference workloads, per R&D World’s account of the comparison. That data-center work eventually fed into Google’s push toward edge-specific silicon, starting with early Coral development boards and continuing through a 2023 partnership with Qualcomm on a RISC-V wearable platform for Wear OS.
The Synaptics collaboration builds directly on that foundation. Google and Synaptics announced their partnership in January 2025, Synaptics launched the Coralboard development platform earlier in 2026, and the companies previewed the resulting Astra chip at Research@ this October, ahead of the formal Tech Day unveiling.
| Date | Milestone |
|---|---|
| 2017 | Google publishes first-generation TPU research paper citing 30-80x performance-per-watt gains |
| 2023 | Google and Qualcomm announce a RISC-V wearable platform for Wear OS |
| January 2025 | Google Research and Synaptics publicly announce their edge AI collaboration |
| Early 2026 | Synaptics launches Coralboard, pairing the Coral NPU with Astra processors for developers |
| October 14, 2026 | Google previews the Coral NPU M2-based Astra chip at Research@ in Mountain View |
| October 20, 2026 | Synaptics plans a formal unveiling at Tech Day in San Jose |
Competitive Landscape: Astra vs. Qualcomm, Ambiq, NXP, and STMicroelectronics
Synaptics is not entering an empty market. Qualcomm remains the volume leader in AI-capable edge silicon, having shipped more than 800 million AI-capable chips in 2025 according to industry data compiled by Axis Intelligence, with Snapdragon platforms using Hexagon NPUs rated at up to 45 TOPS for on-device inference. That positions Qualcomm at the high-performance end of the market, aimed at smartphones and premium wearables that can absorb more power draw than the ultra-constrained devices Synaptics is targeting.
Ambiq, NXP, and STMicroelectronics compete in a different tier, focused on ultra-low-power microcontrollers, embedded processing, and sensor-heavy industrial and automotive applications. Synaptics is trying to carve out space between these two groups, pitching Astra as a highly integrated, ultra-low-power platform that can still handle the multimodal sensing workloads usually reserved for higher-power chips like Qualcomm’s.
| Company | Primary Edge AI Platform | Notable Metric | Market Position |
|---|---|---|---|
| Synaptics | Astra (Coral NPU M2 + Torq NPU + Arm cores) | Claimed <6mW inference, 40% less energy | Ultra-low-power multimodal sensing |
| Qualcomm | Snapdragon (Hexagon NPU) | Up to 45 TOPS, 800M+ AI-capable chips shipped in 2025 | High-performance mobile and wearable AI |
| Ambiq | Apollo microcontroller line | Ultra-low-power MCU focus | Battery-constrained sensor devices |
| NXP | i.MX / eIQ embedded processors | Broad embedded and automotive portfolio | Industrial and automotive edge processing |
| STMicroelectronics | STM32 microcontrollers with AI extensions | Established industrial sensor base | Industrial and automotive sensor fusion |
The Edge AI Chip Market by the Numbers
The timing of Google and Synaptics’ preview lines up with a market that analysts expect to grow quickly. Grand View Research estimates, cited in Axis Intelligence’s 2026 edge AI statistics roundup, value the edge AI chip market at $27.3 billion in 2025, growing to $36.2 billion in 2026. The same estimate projects the market reaching $291.8 billion by 2033, implying a compound annual growth rate of roughly 34.7%. Those figures cover the full edge AI chip category, not Synaptics or Google specifically, but they explain why a company like Synaptics is willing to spend nearly two years co-engineering silicon with a software giant rather than going it alone.
| Year | Edge AI Chip Market Size | Source |
|---|---|---|
| 2025 | $27.3 billion | Grand View Research, via Axis Intelligence |
| 2026 | $36.2 billion (projected) | Grand View Research, via Axis Intelligence |
| 2033 | $291.8 billion (projected) | Grand View Research, via Axis Intelligence |
| 2025-2033 CAGR | Approximately 34.7% | Grand View Research, via Axis Intelligence |
If that growth curve holds, the edge AI chip market would more than triple in size between now and the end of the decade. That kind of expansion tends to pull in more entrants, not fewer, which raises the odds that Synaptics will face new ultra-low-power competitors within the next two or three product cycles rather than a stable five-company field.
What Google and Synaptics Still Haven’t Confirmed
For a chip generating this much coverage, the list of unconfirmed details is long. Neither company has disclosed the transistor count, the manufacturing process node, total on-chip memory capacity, a full-chip TOPS rating, the complete list of supported model architectures, pricing, expected production volume, or the first Google device that will actually ship with the chip inside it. The 40% power claim and the sub-6-milliwatt inference figure are the only hard performance numbers in circulation, and both come without a disclosed testing methodology.
That gap between marketing narrative and verifiable specification is normal for a pre-launch teaser, but it means most of the real analysis has to wait for October 20. Readers and investors treating this preview as a finished product announcement are getting ahead of what Google and Synaptics have actually confirmed.
What to Watch at Synaptics Tech Day on October 20
Synaptics’ Tech Day event in San Jose is where the preview either turns into a credible product or stalls as another unfulfilled chip tease. The company has described a noon press and analyst briefing followed by a demonstration showcase, which suggests working silicon will be on hand rather than simulations or reference designs alone. Analysts will be watching for a full TOPS rating covering the whole chip, confirmed pricing and sampling timelines for OEMs, and ideally a named lead customer or product category beyond the general “Google devices” language Patel used at Research@.
The compiler story also deserves scrutiny at the event. An open, MLIR-based toolchain is only as useful as its documentation and the breadth of model formats it actually supports on day one. If Synaptics ships the chip with a thin software stack and tells developers to wait for tooling updates, the open-compiler pitch will ring hollow regardless of how efficient the underlying silicon turns out to be.
Five Predictions for the Edge AI Chip Race
- Synaptics will likely disclose a full-chip TOPS rating and manufacturing process node at Tech Day on October 20, since withholding both details through a second public appearance would undercut the credibility of the power-efficiency claims.
- Google will probably stay vague about which of its own devices will use the chip for at least one more product cycle, consistent with Patel’s refusal to name specific hardware at Research@.
- Qualcomm, NXP, or STMicroelectronics are likely to respond with their own ultra-low-power NPU announcements within the next two to three quarters, given how directly Synaptics is positioning Astra against the gap between their product tiers.
- The open MLIR compiler approach could pressure other microcontroller vendors to loosen their proprietary software ecosystems, a shift that would play out gradually over 2027 rather than immediately.
- If Grand View Research’s $36.2 billion 2026 market estimate for edge AI chips proves accurate, expect more detailed Astra revenue guidance to show up in Synaptics’ next earnings commentary rather than in marketing materials.
Frequently Asked Questions
What is the Synaptics Astra edge AI chip?
It is a low-power AI processor co-designed by Synaptics and Google Research, combining Google’s Coral NPU M2 with Synaptics’ own Torq NPU and Arm CPU cores. It belongs to Synaptics’ Astra line of AI-native processors and microcontrollers.
When was the chip previewed and when is the full launch?
Google previewed the chip at its Research@ event in Mountain View on October 14, 2026. Synaptics plans to formally unveil it at its Tech Day event in San Jose on October 20, 2026.
How much power does the chip actually save?
Synaptics and Google say the Coral NPU M2 uses 40% less energy than existing processors and can run on-device inference at an average draw of less than 6 milliwatts. Neither company has disclosed the specific baseline chip or workload used for that comparison.
Will the chip ship inside Google devices?
Synaptics CEO Rahul Patel said the chip will be built into Google devices, but neither company has named specific products or given a shipping timeline.
What devices is this chip designed for?
Target applications include wearables, smart glasses, connected cameras, and industrial vision and voice systems, which is any device where cloud-dependent AI processing adds too much latency or drains too much battery.
How does this compare to Qualcomm’s edge AI chips?
Qualcomm’s Snapdragon platforms use Hexagon NPUs rated at up to 45 TOPS and shipped in more than 800 million AI-capable chips in 2025, targeting higher-power smartphones and premium wearables. Synaptics is targeting an even lower power tier aimed at multimodal sensing on far more constrained devices.
Is there a successor chip already planned?
Google has said its next Coral design, M3, is already complete and adds native 32-bit floating-point support to run Gemma 3 270M, a 270-million-parameter language model, directly on-device. No shipping date for M3-based silicon has been announced.